Semicon 2.0 Gets Chip Design and Talent Right; Governance Is the Risk

The Lift Line

A semiconductor policy that lets its bureaucracy take venture-grade risk is one that means to build fabs.

Why This Editorial Matters for Your Exam

Semicon 2.0 is now the anchor scheme for a Mains answer on India’s semiconductor policy, industrial policy design and public-equity risk management. This piece supplies the exact numbers, from the 30 to 40 per cent band to the ten categories to the 75 per cent research and talent backing, that will separate a middle-band answer from a top-band one. The C-DAC co-ownership problem in the defence category is a distinctive analytical hook.

GS Paper 3: Indian Economy; issues relating to planning, mobilization of resources; effects of liberalization on the economy, changes in industrial policy; science and technology, indigenisation of technology.

Background and Context

This is a signed opinion column by Pranay Kotasthane of the Takshashila Institution, writing in a personal capacity. The argument below is his, not the newspaper’s editorial line.

Semicon 2.0 came in two steps. As background, the Union Cabinet approved the India Semiconductor Mission 2.0 outlay of about Rs 1,27,500 crore on 15 July 2026, more than double Semicon 1.0’s Rs 76,000 crore. On 31 August 2026, the Ministry of Electronics and Information Technology (MEITy) then notified Semicon 2.0, an overhaul of India’s semiconductor incentive architecture. Four things stand out. Chip design, for the first time, is front and centre; the India Semiconductor Mission (ISM) now runs both design and manufacturing (design was earlier with the Centre for Development of Advanced Computing (C-DAC)); research and talent development get specified fiscal backing; and upfront capex support across manufacturing has been recalibrated into a 30 to 40 per cent band from Semicon 1.0’s uniform 50 per cent.

The Analysis

1. From four notifications to one instrument. Semicon 1.0, notified in 2021, arrived as four separate schemes: a design-linked incentive, a compound-semiconductor and packaging scheme, a display-fab scheme, and a silicon-fab scheme. Semicon 2.0 folds the whole value chain into one instrument with six pillars and ten categories, spanning design, materials, fabrication, packaging, research and talent. A single instrument permits coherent industrial-policy trade-offs; separate notifications did not.

2. Chip design at the front is a bet on India’s real advantage. India’s comparative advantage in the global semiconductor value chain is design talent. Semicon 1.0’s design-linked incentive worked through reimbursement, capped at Rs 15 crore, with a deployment incentive on total sales. It did not match an industry where gestation runs to five years; only 24 of 100 target firms received the fiscal support.

3. The hybrid capital stack fits the industry. Semicon 2.0 replaces reimbursement with a mix. Seed funding up to Rs 15 crore; then, once a startup has raised private venture capital, equity co-investment or royalty financing. Startups now have grant, equity and royalty options rather than a single reimbursement route. The scheme also drops the numeric cap on foreign shareholding, replacing it with a control test requiring the company to remain owned and controlled by Indian citizens or Overseas Citizens of India. Indian startups can bid in consortium mode with global companies, R&D organisations and academic institutions.

4. The control test is a partial reform. An eligible startup can raise as much foreign capital as investors are willing to put in, but only up to the point where citizens or OCIs still control the company. This is a reasonable compromise between attracting capital and avoiding a foreign-controlled recipient of public money. It stops short of a fuller reform in which support goes to any India-registered company regardless of ownership, since design capability matters more than who holds the equity.

5. The equity model raises a real second problem. Venture investing assumes that most bets fail outright and a few big wins cover the rest. Government finance treats the loss of public money as a presumption of impropriety. Bureaucrats negotiating valuations and write-downs under that scrutiny will be structurally biased toward caution, exactly the opposite of what deep-tech investing needs. One fix is for the state to hold equity with no say in company decisions, leaving private investors to negotiate the actual terms; guidelines on this will show in the operationalisation.

6. The defence-chip category creates its own conflict. For defence and critical-infrastructure chips (including telecom), C-DAC selects firms via competitive bidding, and the resulting intellectual property is co-owned with C-DAC. This is meant to keep sovereign IP out of foreign hands and to counter export-control blockades. But global venture capital underwrites bets on unencumbered IP, and a state co-owner makes the venture nearly non-fundable by private investors. In practice, this category will likely stay the preserve of defence contractors and state-backed consortia. Since C-DAC runs the bidding and ends up co-owning the selection, the conflict of interest remains.

7. The materials and packaging pillars address the two weak links. Pillar 2 offers 30 per cent capex support plus a production-linked incentive of 2 to 10 per cent on domestic bill-of-materials sourcing from FY29, funding the ultra-pure supply chain that fabs previously lacked. Pillar 3 carries fab support forward with the quantum trimmed: future silicon wafer fabs at 40 per cent upfront capital against the earlier 50 per cent, compound-semiconductor, photonics and display fabs at 35 per cent. Pillar 4, packaging, offers 35 per cent upfront capital for advanced 2.5D and 3D packaging against 25 per cent for legacy work, playing to a comparative advantage: nine assembly and testing plants are already approved under Semicon 1.0.

8. Research and talent are the sharpest fix. India’s public labs have historically received capital grants for expensive equipment and no operating budget to run it. Semicon 2.0 funds up to 75 per cent of both. This is the structural gap Semicon 1.0 left standing, and Semicon 2.0 is now the first Indian scheme to price research operating costs as first-class citizens rather than as afterthoughts.

Data and Institutions Vault

Prelims-grade facts:

The scheme, in numbers:

• Semicon 2.0 was notified by MEITy on 31 August 2026, consolidating Semicon 1.0’s four separate 2021 notifications into a single instrument with six pillars and ten categories.
• The India Semiconductor Mission (ISM) now runs both design and manufacturing; design was earlier with the Centre for Development of Advanced Computing (C-DAC).
• Upfront capex has been recalibrated from Semicon 1.0’s uniform 50 per cent to a 30 to 40 per cent band; silicon wafer fabs get 40 per cent, compound-semiconductor, photonics and display fabs get 35 per cent.
• Advanced 2.5D and 3D packaging gets 35 per cent capex; legacy packaging gets 25 per cent.
• Pillar 2 (materials and equipment) offers 30 per cent capex plus a PLI of 2-10 per cent on domestic bill-of-materials sourcing from FY29.
• Research and talent (pillars 5 and 6) get up to 75 per cent fiscal backing on both equipment and operating costs.

The design-linked incentive:

• Semicon 1.0’s DLI capped support at Rs 15 crore per firm on reimbursement basis; only 24 of a target 100 firms received support.
• Semicon 2.0’s DLI: seed funding up to Rs 15 crore, then equity co-investment or royalty financing after private VC is raised.
• The foreign shareholding numeric cap is dropped in favour of a control test requiring Indian citizen or OCI control.

The institutional architecture:

• MEITy (Ministry of Electronics and Information Technology) is the nodal ministry.
• India Semiconductor Mission (ISM) sits within Digital India Corporation under MEITy.
• C-DAC (Centre for Development of Advanced Computing), Pune-headquartered, is the R&D arm under MEITy.
• Under Semicon 1.0, nine ATMP (Assembly, Testing, Marking and Packaging) plants were approved.

The global context:

• The global semiconductor market is largely concentrated in Taiwan (TSMC), South Korea (Samsung, SK Hynix), the United States (Intel, Nvidia design), the Netherlands (ASML lithography) and Japan (materials and equipment).
• India’s target for the electronics sector is a USD 500 billion market by 2030.

Watch the trap: ISM and C-DAC are both under MEITy, but they have different mandates. ISM runs the mission; C-DAC is an R&D arm that also handles the defence-chip bidding under Semicon 2.0, which creates the conflict-of-interest concern.

A second trap: Pillar 3 (fabs) covers silicon, compound-semiconductor, photonics and display fabs; Pillar 4 (packaging) covers ATMP. The two are consecutive stages of the value chain, not alternatives.

The Debate

FOR the Semicon 2.0 design: Chip design at the front, ISM running the whole value chain, a hybrid capital stack replacing reimbursement, dropped foreign-shareholding numeric caps, funded research and talent operating costs, and calibrated fab support are all corrections of Semicon 1.0’s weakest links. This is a substantially better scheme than the one it replaces.

AGAINST the design as it stands: ISM now runs ten categories, equity management, royalty tracking and investment decisions; the administrative load is enormous and the scheme’s success depends on a step-jump in ministry capacity. The equity model will produce failures that vigilance will treat as impropriety. The C-DAC co-ownership in the defence category creates a foreign-investment repellent and a conflict of interest that no design will fully cure.

Balanced verdict: Semicon 2.0 is a definite improvement, and its execution risk is administrative rather than conceptual. The fixes are known: state equity without company-decision rights, statutory shielding of write-downs, ISM statutory footing, and separation of C-DAC’s bidder and IP-co-owner roles. Whether they are made is the whole question.

How to Think About This

For any industrial-policy scheme, ask four questions. What is the target industry’s real comparative advantage? Does the incentive design match the industry’s gestation and risk profile? Where is the state’s money at risk, and how is that risk protected from a vigilance-first framework? What administrative capacity does the scheme presume, and does it exist? Semicon 2.0 answers the first two well; the third and fourth are its execution risks.

Diagram-in-Words

PYQ Linkage

• UPSC CSE Mains 2022, GS3: “What are the different elements of cyber security? Keeping in view the challenges in cyber security, examine the extent to which India has successfully developed a comprehensive National Cyber Security Strategy.” Different subject; same industrial-policy design frame.
• UPSC CSE Mains 2019, GS1: “How can the mountain ecosystem be restored from the negative impact of development initiatives and tourism?” Very different subject; same how-to-design-a-scheme discipline.
• UPSC CSE Mains 2019, GS3: “It is argued that the strategy of inclusive growth is intended to meet the objectives of inclusiveness and sustainability together. Comment on this statement.” Direct on the industrial-policy angle.

Sources: Hindustan Times, Ministry of Electronics and IT, India Semiconductor Mission

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