India Needs the Right Chips: Semiconductors and ISM 2.0

Source: Original editorial ↗ The Indian Express

The Lift Line

“The countries that write the story of this century will be those that design the chips the world runs on.”

Why This Editorial Matters for Your Exam

Rajeev Chandrasekhar, former Minister of State for Electronics and Information Technology, who helped design the India Semiconductor Mission and is now the BJP’s Kerala State president, argues in The Indian Express of 2 October 2026 that India’s chip push is too heavily weighted towards low-margin assembly and testing. It is a ready-made framework for GS3 questions on industrial policy, technology sovereignty and value chains. Read it as an insider’s view of a programme he helped shape.

GS Paper 3: Science and technology: indigenisation of technology; industrial policy; effects of liberalisation on industry.

Background and Context

The semiconductor value chain.

Stage	What happens	Margins and character
Design	Chip architecture and IP; “fabless” firms design, others manufacture	50 to 70% gross margins for IP-owning design, the writer says
Fabrication (fab)	Wafers made in clean rooms	Very capital-intensive; concentrated in Taiwan, South Korea, US
ATMP / OSAT	Assembly, testing, marking and packaging; outsourced assembly and test	Wire-bond packaging about 6% margins; advanced packaging 25 to 35%

India’s programmes.

Programme	Feature
India Semiconductor Mission (ISM)	Launched December 2021 with Rs 76,000 crore for fabs, display fabs, ATMP/OSAT and design
Design Linked Incentive (DLI)	Support for chip design start-ups and MSMEs
DIR-V	Digital India RISC-V programme for indigenous processors on an open instruction set
IndiaAI Mission	Compute capacity, datasets and foundation models
ISM 2.0	Further Rs 1.275 lakh crore, the writer says

The Analysis

1. Foundations, not destinations. ISM, DLI and IndiaAI were the right first moves. The question now is the second set of moves.

2. A skewed portfolio. Of 12 approved units with Rs 1.64 lakh crore committed, nine are conventional ATMP/OSAT facilities, the most substitutable segment, the writer says.

3. Wrong analogy. The electronics PLI worked because Apple and Samsung wanted to diversify from China; India now assembles 25 to 28 per cent of iPhones. But semiconductors are going through an architectural revolution driven by AI, not a supply-chain shift.

4. Inference is the opening. Training chips are consolidating around Nvidia’s CUDA ecosystem and hyperscalers’ own chips. Inference needs are too varied for one architecture, so purpose-built chips can win. India has about 1,25,000 chip design engineers.

5. What to fund. A National Semiconductor Research Institute; an expanded DLI; a Rs 1,000 crore Chip Design Commercialisation Fund modelled on NIIF; and two sovereign AI inference chip programmes with guaranteed government offtake.

Data and Institutions Vault

Prelims-grade facts:

India’s programmes:

• India Semiconductor Mission: launched December 2021, outlay Rs 76,000 crore; under MeitY.
• DIR-V: Digital India programme for processors based on the open RISC-V instruction set.
• IndiaAI Mission: approved 2024; compute, datasets, foundation models.

Global comparisons (as cited by the writer):

• US CHIPS Act: $53 billion in direct subsidy.
• China: about $150 billion for chip self-sufficiency since 2015.

Terms:

• ATMP/OSAT: assembly, testing, marking and packaging / outsourced semiconductor assembly and test.
• Fabless: firms that design chips but outsource manufacture.
• Tape-out: the final design sent for manufacture.

⚠️ Watch the trap: RISC-V is an open-standard instruction set architecture, free of licence fees; ARM is a licensed architecture. RISC-V is not a chip or a company.

The Debate

For the writer’s view. Value and strategic leverage lie in design and IP; investment counts can hide a weak position.

The complications. Assembly and packaging are how Taiwan, Malaysia and others built ecosystems; design firms need access to fabs; and guaranteed offtake for state-backed chips risks picking winners.

The balanced verdict. Build the base and climb the ladder at the same time, and measure success by IP owned and value added in India.

How to Think About This

Ask where the value sits. In any value chain question, map the stages, their margins and who controls the IP. Policy that maximises investment commitments may still leave a country in the lowest-margin stage.

Diagram-in-Words

Takeaway Box

• Problem: most approved units are low-margin ATMP/OSAT.
• Opportunity: AI inference chips and advanced packaging.
• Assets: about 1,25,000 design engineers, DIR-V (RISC-V), domestic demand.
• Asks: research institute, design commercialisation fund, government offtake.

Sources: The Indian Express, India Semiconductor Mission, MeitY

Source: India Needs the Right Chips: Semiconductors and ISM 2.0 — Ujiyari.com | Free UPSC & State PCS Editorial Analysis

Key Arguments at a Glance

Rajeev Chandrasekhar argues that India’s semiconductor push has laid the right foundations but is concentrated in low-margin assembly, testing, marking and packaging, and that the second phase of the India Semiconductor Mission should fund chip design, advanced packaging, research and AI inference chips.

✓ Supporting

• At SEMICON India 2026, 12 units were approved with Rs 1.64 lakh crore committed and five in production, and ISM 2.0 adds Rs 1.275 lakh crore, the writer says; but nine of the 12 are conventional ATMP/OSAT units in the lowest-margin segment.
• The electronics PLI succeeded on China-plus-one logic (India now assembles 25 to 28% of iPhones), but semiconductors are undergoing an architectural revolution, not a supply-chain shift; wire-bond packaging earns about 6% gross margins against 50 to 70% in IP-owning chip design.
• AI training chips are consolidating around Nvidia’s CUDA ecosystem and hyperscalers’ custom chips, but inference chips for cloud, edge, defence and industry are wide open, and India has about 1,25,000 chip design engineers and the DIR-V RISC-V programme.
• Missing pieces: a National Semiconductor Research Institute, capital to take fabless firms to commercial tape-out, an expanded Design Linked Incentive, a Rs 1,000 crore Chip Design Commercialisation Fund and two sovereign AI inference chip programmes with government offtake.

⚠ Counter

Ujiyari’s synthesis: assembly and packaging build the skills, supplier base and ecosystem that design and fabrication later need, as in Malaysia and Taiwan’s history; design firms also need fabs, and betting on two government-backed inference chips risks picking winners in a fast-moving market.

→ Way Forward

The writer proposes redirecting ISM 2.0 toward design IP, advanced packaging (CoWoS-type integration), a national research institute and guaranteed public procurement for Indian inference chips. Ujiyari adds: measure the mission by value added and IP created in India, not by investment commitments.